CHIP PACKAGE AND METHOD FOR FORMING THE SAME

摘要

An embodiment of the invention provides a chip package which includes a first substrate including a device region and having a first surface and a second surface opposite thereto. A dielectric layer is disposed on the second surface of the first substrate and includes a conducting pad structure connected to the device region, and the first substrate completely covers the conducting pad structure. A second substrate is disposed on the second surface of the first substrate and the dielectric layer is located between the first substrate and the second substrate. The second substrate has a first opening exposing a surface of the conducting pad structure, and a redistribution layer is conformally disposed on a sidewall of the first opening and the surface of the exposed conducting pad structure. A method for forming the chip package is also provided.

主权项

1. A chip package, comprising:
a first substrate comprising a device region and having a first surface and a second surface opposite thereto; a dielectric layer disposed on the second surface of the first substrate, wherein the dielectric layer comprises a conducting pad structure electrically connected to the device region, and wherein the first substrate completely covers the conducting pad structure; a second substrate disposed on the second surface of the first substrate, wherein the dielectric layer is located between the first substrate and the second substrate, and wherein the second substrate has a first opening exposing a surface of the conducting pad structure; and a redistribution layer conformally disposed on a sidewall of the first opening and the surface of the exposed conducting pad structure.