ADAPTIVE CARTESIAN LOOP TRANSMITTER FOR BROADBAND AND OPTIMAL LOOP STABILITY ADJUSTMENT

摘要

An integrated circuit includes a linearizer circuit in which excessive delay is compensated. The linearizer circuit includes a power amplifier, forward and feedback paths, and a microprocessor. A signal from the power amplifier is routed by the forward path to be transmitted while a portion of the signal to be transmitted is routed back to the power amplifier via the feedback path. The microprocessor applies phase training signals to the forward path. The microprocessor uses the phase training signals to determine the amount of delay in the linearizer circuit and alters the frequency position of poles and zeros in the linearizer circuit to compensate for the delay. The gain of the linearizer circuit is also altered by the microprocessor depending on the measured delay.