| 摘要 |
Apparatus 2 for processing data has fetch circuitry 16 for fetching program 5 instructions for execution from one or more active threads of instructions having respective program counter values. Pipeline circuitry 22, 24 has a first operating mode and a second operating mode. At least one portion of the pipeline circuitry is disabled in one of the modes and enabled in a different one of the modes. Mode switching circuitry 30 switches the pipeline circuitry between the first and second operating modes in dependence upon a number of active threads of program instructions having program instructions available to be executed. The first operating mode may use barrel processing pipeline 22 to perform interleaved multiple thread processing and has a lower average energy consumption per instruction executed than the second operating mode. The second operating mode may utilise an out-of-order processing pipeline 24 for performing out-of-order processing has a higher average rate of instruction execution for a single thread than the first operating mode. Alternatively, shared pipeline circuitry (72, fig. 4) may be operated in the first mode for interleaved multiple threaded operation and the second mode for single threaded operation. |
