| 发明名称 | Low-latency high-gain current-mode logic slicer | ||
| 摘要 | A low-latency, high-gain (LLHG) slicer includes an input stage coupled to a differential output port and configured to receive a differential analog input signal, and to track the differential analog input signal during a tracking phase, an output stage coupled to the differential output port and configured to generate digital output bits corresponding to the differential analog input signal during a regeneration phase, and a tunable resistor coupled to the differential output port and configured to provide a first load impedance during the tracking phase and to provide a second load impedance during the regeneration phase, the first load impedance being lower than the second load impedance. | ||
| 申请公布号 | US9595975(B1) | 申请公布日期 | 2017.03.14 |
| 申请号 | US201615144521 | 申请日期 | 2016.05.02 |
| 申请人 | Samsung Display Co., Ltd. | 发明人 | Song Sanquan;Amirkhany Amir |
| 分类号 | H03H7/40;H03M1/12;H03K19/0944 | 主分类号 | H03H7/40 |
| 代理机构 | Lewis Roca Rothgerber Christie, LLP | 代理人 | Lewis Roca Rothgerber Christie, LLP |
| 主权项 | 1. A low-latency, high-gain (LLHG) slicer comprising: an input stage coupled to a differential output port and configured to receive a differential analog input signal, and to track the differential analog input signal during a tracking phase; an output stage coupled to the differential output port and configured to generate digital output bits corresponding to the differential analog input signal during a regeneration phase; and a tunable resistor coupled to the differential output port and configured to provide a first load impedance during the tracking phase and to provide a second load impedance during the regeneration phase, the first load impedance being lower than the second load impedance. | ||
| 地址 | Yongin-si KR | ||