Clock routing techniques

摘要

Techniques are disclosed relating to clock routing techniques in processors with both pipelined and non-pipelined circuitry. In some embodiments, an apparatus includes execution units that are non-pipelined and configured to perform instructions without receiving a clock signal. In these embodiments, one or more clock lines routed throughout the apparatus do not extend into the one or more execution units in each pipeline, reducing the length of the clock lines. In some embodiments, the apparatus includes multiple such pipelines arranged in an array, with the execution units located on an outer portion of the array and clocked control circuitry located on an inner portion of the array. In some embodiments, clock lines do not extend into the outer portion of the array. In some embodiments, the array includes one or more rows of execution units. These arrangements may further reduce the length of clock lines.

主权项

1. An apparatus, comprising:
a plurality of execution pipelines physically located in at least first and second rows such that there is an intermediate region between the first and second rows, wherein the plurality of execution pipelines are arranged such that each of the plurality of execution pipelines has an inner portion that is closer to the intermediate region than an outer portion of that execution pipeline, wherein each of the plurality of execution pipelines comprises:
pipelined circuitry physically located in the inner portion of that execution pipeline and configured to operate based on a clock signal; andone or more execution units physically located in the outer portion of that execution pipeline and configured to perform an operation without receiving a clock signal; and one or more clock lines configured to provide the clock signal, wherein the one or more clock lines are physically routed through the intermediate region and extend into the pipelined circuitry but do not extend into the one or more execution units.