Facilitation of increased locking range transistors

摘要

Transistors can be used for a variety of electronic-based applications. Therefore, transistor efficiency and performance is of importance. An apparatus is presented herein to increase the locking range of transistors by leveraging cross-coupled injection transistors in conjunction with symmetry injection transistors. The transistor efficiency can also be increase by reducing a parasitic capacitance associated with the components of the transistor.

主权项

1. An apparatus, comprising:
a first injection transistor comprising a first source; a second injection transistor comprising a second source, wherein the first injection transistor and the second injection transistor are cross coupled, and wherein the first source and the second source are connected to a first ground; a first symmetry injection transistor comprising a third source; a second symmetry injection transistor comprising a fourth source, wherein the third source and the fourth source are connected to a second ground, wherein the first symmetry injection transistor, the second symmetry injection transistor, the first injection transistor, and the second injection transistor are formed on a single transistor cell, and wherein a transistor width of a transistor of at least one of the first symmetry injection transistor, the second symmetry injection transistor, the first injection transistor, or the second injection transistor varies from that of another transistor width of a different transistor of the at least one of the first symmetry injection transistor, the second symmetry injection transistor, the first injection transistor, or the second injection transistor; a first node comprising:
a first drain of the first injection transistor;a first gate of the second injection transistor; anda second drain of the first symmetry injection transistor; a second node comprising:
a third drain of the second injection transistor;a second gate of the first injection transistor; anda fourth drain of the second symmetry injection transistor; and a third node comprising:
a third gate of the first symmetry injection transistor; anda fourth gate of the second symmetry injection transistor.