DOUBLE CONSECUTIVE ERROR CORRECTION

摘要

Described is a processor with a data storage structure operative to store data and a first error correction code that corresponds to the data. The processor further includes circuitry to compare the first and second error correction codes to obtain a comparison result. There are no errors in the data when the comparison result is equal to zero and there is at least one error in the data when the comparison result is not equal to zero. The circuitry corrects a single bit error of the data when the comparison result matches one of the unique combination of bit values of one of the plurality of bit groups in the generator matrix and corrects two consecutive data bits of the data when the comparison result corresponds to a predefined number of values as a result of an exclusive-or (XOR) operation performed on two consecutive bit groups of the generator matrix.

主权项

1. A user equipment (UE) comprising:
a peripheral device; a memory device; and a System on Chip (SoC) coupled to the peripheral device and the memory device, wherein the SoC comprises:
a data storage structure to store a set of data and a first error correction code that corresponds to the set of data, wherein the set of data comprises a plurality of data bits, wherein the first error correction code was generated using a generator matrix having a plurality of bit groups, each bit group comprising a unique combination of bit values;a comparator to generate a comparison result of the first error correction code and a second error correction code, wherein the second error correction code is generated based on the generator matrix, wherein there are no errors in the set of data when the comparison result is equal to zero, wherein there is at least one error in the set of data when the comparison result is not equal to zero; anda data corrector to i) correct a single bit error of the set of data when the comparison result matches one of the unique combination of bit values of one of the plurality of bit groups in the generator matrix; and ii) correct two consecutive data bits of the set of data when the comparison result corresponds to a predefined number of values as a result of an exclusive-or (XOR) operation performed on two consecutive bit groups of the generator matrix.