发明名称 MULTIPHASE CLOCK DATA RECOVERY FOR A 3-PHASE INTERFACE
摘要 Methods, apparatus, and systems for data communication over a multi-wire, multi-phase interface are disclosed. A method of data communication includes configuring a clock recovery circuit to provide a first clock signal that includes a pulse for each symbol transmitted on the interface, where symbols are transmitted on the interface at a first frequency, adjusting a loop delay of the clock recovery circuit to modify the first clock to have a second frequency that is no more that half the first frequency, where the clock recovery circuit generates a pulse in the first clock signal for a first of an integer number of symbols and suppresses pulse generation for other symbols in the integer number of symbols, configuring a clock generation circuit to provide a second clock signal, and capturing symbols from the interface using the first clock signal and the second clock signal.
申请公布号 WO2017039985(A1) 申请公布日期 2017.03.09
申请号 WO2016US46211 申请日期 2016.08.09
申请人 QUALCOMM INCORPORATED 发明人 DUAN, Ying;LEE, Chulkyu;CHOU, Shih-Wei;DANG, Harry;KWON, Ohjoon
分类号 H04L7/033;H04L25/49 主分类号 H04L7/033
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