| 摘要 |
PURPOSE:To provide the semiconductor integrated circuit which consists of a large scale and can be operated at a high speed without being restricted by a clock skew. CONSTITUTION:Each processing circuit 11a, 11b is provided with clock generators 12a, 12b, and FIFO memories 13a, 13b for reading out store data to the processing circuits 11a, 11b by a clock signal from these clock generators 12a, 12b, and storing output data of the processing circuits 11a, 11b of the pre-stage by a clock signal from the pre-stage. Accordingly, it is unnecessary to provide a clock driver having large driving force for driving a clock wiring extending over the whole chip as before, and also, it is unnecessary to execute a timing verification for considering arrangement of each block and wiring length between the blocks, and a high speed operation can be executed by a large-scale circuit without being restricted by a clock skew. |
