SYSTEMS AND METHODS FOR IMPLEMENTING ERROR CORRECTING CODE IN A MEMORY

摘要

Systems and methods are disclosed for error correction control (ECC) for a memory device comprising a data portion and an ECC portion, the memory device coupled to a system on a chip (SoC). The SoC includes an ECC cache. On receipt of a request to write a line of data to the memory, a determination is made if the data is compressible. If so, the data line is compressed. ECC bits are generated for the compressed or uncompressed data line. A determination is made if an ECC cache line is associated with the received data line. If the data line is compressible, the ECC bits are appended to the compressed data line and the appended data line is stored in the data portion of the memory. Otherwise, the ECC bits are stored in the ECC cache and the data line is stored in the data portion of the memory.

主权项

1. A method for implementing error correction control (ECC) in a memory device, the method comprising:
receiving a request at a component of a system on a chip (SoC), to write a data line to a memory device in electrical communication with the SoC; determining if the received data line is compressible; determining if there is a hit or a miss for a cache line of an ECC cache of the SoC associated with the received data line; and responsive to a determination that the received data line is compressible:
compressing the received data line, generating ECC bits based on the compressed data line, appending the ECC bits to the compressed data line, storing the appended compressed data line in a data portion of the memory device, and
responsive to a hit for the ECC cache, deleting the cache line of the ECC cache associated with the received data line, orresponsive to a miss for the ECC cache, determining whether to delete a line of an ECC portion of the memory device, or, responsive to a determination that the received data line is not compressible:
generating ECC bits based on the uncompressed data line, storing the uncompressed data line in the data portion of the memory device, and writing the generated ECC bits to the ECC cache.