INTEGRATED CIRCUIT PACKAGE COMPRISING SURFACE CAPACITOR AND GROUND PLANE

摘要

Many aspects of an improved IC package are disclosed herein. The improved IC package exhibits low-impedance and high power and signal integrity. The improved IC package comprises an IC die mounted on a multilayer coreless substrate. The thicknesses of prepreg layers of the coreless substrate are specific chosen to minimize warpage and to provide good mechanical performance. Each of the prepreg layers may have different coefficient of thermal expansion (CTE) and/or thickness to enable better control of the coreless substrate mechanical properties. The improved IC package also includes a vertically mounted die side capacitor and a conductive layer formed on the solder resist layer of the substrate. The conductive layer is formed such that it also encapsulates the vertically mounted capacitor while being electrically coupled to one of the capacitor's electrode.

主权项

1. An integrated circuit package comprising:
an integrated circuit die coupled to a first plurality of substrate pads embedded in a first layer of a substrate; a vertical capacitor having a first electrode coupled to a first substrate pad embedded in the first layer of the substrate; and a conductive layer formed on a first surface and a second electrode of the vertical capacitor, wherein the conductive layer encapsulates the vertical capacitor, and wherein the first and second electrodes are parallel to each other and perpendicular to a planar surface of the substrate.