发明名称 ARRANGEMENT PROCESSING SYSTEM FOR LOGIC CIRCUIT DIAGRAM
摘要 PURPOSE:To prevent a flow of logic from being parted, by comparing a circuit configuration conforming with a circuit model which has been given in advance by a circuit model table, by a logical connection table, and placing it as a logical macro-symbol, in case of placing a logical symbol. CONSTITUTION:A logical connection table 2 has information such as a logical function name, a logical symbol size, the number of input/output pins, a pointer to a pin table, a pointer between logical symbols, etc., in a symbol table 201, and has information such as a pin number, and a pointer between pins being in a connected relation, etc., in a pin table 202, and a circuit model table 3 has a logical macro-name, a logical macro-symbol size, the number of input/ output pins, a pointer to a symbol table 302, and the number of components, etc., in a model table 301. In this way, in case of placing the logical symbol, a circuit configuration conforming with a circuit model which has been determined in advance by the circuit model table is compared by the logical connection table, and place as a logical macro-symbol.
申请公布号 JPS62287372(A) 申请公布日期 1987.12.14
申请号 JP19860132144 申请日期 1986.06.06
申请人 NEC CORP 发明人 HORIUCHI SHINICHI
分类号 H03K19/00;G06F17/50 主分类号 H03K19/00
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