| 摘要 |
A semiconductor device capable of reducing an inter-source electrode resistance RSS(on) and reducing a chip size is provided. A semiconductor device according to the present invention includes a chip partitioned into three areas including a first area, a second area, and a third area, and a common drain electrode provided on a back surface of the chip, in which the second area is formed between the first and third areas, a first MOSFET is formed in the first area and the third area, and a second MOSFET is formed in the second area. |
| 主权项 |
1. A semiconductor device comprising:
a chip partitioned into three areas including a first area, a second area, and a third area; and a common drain electrode provided on a back surface of the chip, wherein: the second area is formed between the first area and the third area such that the first area is spaced apart from the third area, in plan view, a first MOSFET is formed in the first area and the third area, a second MOSFET is formed in the second area, all pads formed on a front surface of the chip are arranged to form only three lines of pads including a first line, a second line and a third line, the first line is formed in the first area, the second line is formed in the second area, the third line is formed in the third area, each of the pads of the first to third lines is connected to one of a gate and a source of one of the first MOSFET and the second MOSFET, the pads include a first gate pad and a second gate pad, the first gate pad disposed in the first area, the first gate pad being electrically connected to the first MOSFET, the second gate pad disposed in the third area, the second gate pad being electrically connected to the second MOSFET, each of the first, second and third areas includes two source pads of the six source pads, and each of the first and second gate pads is disposed so as to be sandwiched between the two source pads. |
