Semiconductor device having fin-shaped semiconductor layer

摘要

An SGT production method includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film; a second step of forming a pillar-shaped semiconductor layer, a first dummy gate, and a first hard mask formed from a third insulating film; a third step of forming a second hard mask on a side wall of the first hard mask, and forming a second dummy gate; a fourth step of forming a sidewall and forming a second diffusion layer; a fifth step of depositing an interlayer insulating film, exposing upper portions of the second dummy gate and the first dummy gate, removing the second dummy gate and the first dummy gate, forming a first gate insulating film, and forming a gate electrode and a gate line; and a sixth step of forming a first contact and a second contact.

主权项

1. A semiconductor device, comprising:
a fin-shaped semiconductor layer formed on a semiconductor substrate; a first insulating film formed around said fin-shaped semiconductor layer; a pillar-shaped semiconductor layer formed on said fin-shaped semiconductor layer; a first gate insulating film formed around said pillar-shaped semiconductor layer; a gate electrode formed of metal and formed around said first gate insulating film; a gate line formed of metal connected to said gate electrode, and extending in a direction orthogonal to said fin-shaped semiconductor layer, and said first gate insulating film being formed around and under said gate electrode and said gate line; a second diffusion layer formed in an upper portion of said fin-shaped semiconductor layer and in a lower portion of said pillar-shaped semiconductor layer; a second gate insulating film formed around an upper side wall of said pillar-shaped semiconductor layer; and a first contact formed around said second gate insulating film and formed of a second metal, said gate electrode and said gate line having a top surface and a bottom surface, said top surface of said gate electrode and said gate line having a larger area than said bottom surface of said gate electrode and said gate line; and an upper portion of said first contact being connected to an upper portion of said pillar-shaped semiconductor layer.