发明名称 Transistors having strained channel under gate in a recess
摘要 Some embodiments include a construction having a second semiconductor material over a first semiconductor material. A region of the second semiconductor material proximate the first semiconductor material has strain due to different lattice characteristics of the first and second semiconductor materials. A transistor gate extends downwardly into the second semiconductor material. Gate dielectric material is along sidewalls and a bottom of the transistor gate. Source/drain regions are along the sidewalls of the transistor gate, and the gate dielectric material is between the source/drain regions and the transistor gate. A channel region extends between the source/drain regions and is under the bottom of the transistor gate. At least some of the channel region is within the strained region.
申请公布号 US9640656(B2) 申请公布日期 2017.05.02
申请号 US201414245092 申请日期 2014.04.04
申请人 Micron Technology, Inc. 发明人 Mayuzumi Satoru;Fischer Mark
分类号 H01L29/78;H01L27/105;H01L29/08;H01L29/165;H01L29/423;H01L29/66;H01L29/10;H01L27/088;H01L29/267;H01L27/108 主分类号 H01L29/78
代理机构 Wells St. John P.S. 代理人 Wells St. John P.S.
主权项 1. A semiconductor construction, comprising: a first semiconductor material; a second semiconductor material over the first semiconductor material and having a strained region proximate the first semiconductor material due to different lattice characteristics of the first and second semiconductor materials; a transistor gate extending downwardly into the second semiconductor material; gate dielectric material along sidewalls and a bottom of the transistor gate; source/drain regions along the sidewalls of the transistor gate, the gate dielectric material being between the source/drain regions and the transistor gate; wherein a channel region extends between the source/drain regions and under the bottom of the transistor gate, at least some of the channel region being within the strained region; and wherein the source/drain regions are less deep than the transistor gate within the second semiconductor material.
地址 Boise ID US