发明名称 |
Scan Chain Circuits In Non-Volatile Memory |
摘要 |
A bit scan circuit includes N scan blocks corresponding with an N-bit string of binary data. The string is scanned using an input clock signal to count the number of bits having a predetermined binary value. Each scan block includes a single latch to transfer the corresponding bit and to indicate reset. The scan blocks are organized into groups. Each group is enabled by a corresponding token signal. The token signal for each group is asserted after each preceding scan block indicates a pass value. When enabled by its token signal, the first scan block in a group is reset by a first clock signal. A second scan block in the group is enabled for reset after the first scan block indicates the pass value. The second scan block in the group is reset by a second clock signal having pulses that precede corresponding pulses from the first clock signal. |
申请公布号 |
US2017115342(A1) |
申请公布日期 |
2017.04.27 |
申请号 |
US201514919154 |
申请日期 |
2015.10.21 |
申请人 |
SanDisk 3D LLC |
发明人 |
Wang Kesheng |
分类号 |
G01R31/3177;G01R31/317;G11C16/04 |
主分类号 |
G01R31/3177 |
代理机构 |
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代理人 |
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主权项 |
1. An apparatus, comprising:
a plurality of scan block groups comprising a scan chain for a string of binary data, wherein each scan block group includes a first scan block having a tag bit and a second scan block having a tag bit, the first scan block of each scan block group coupled to a first clock signal and the second scan block of each scan block group coupled to a second clock signal; and a plurality of token latches, each token latch coupled to a corresponding scan block group and configured to enable the corresponding scan block group in response to the tag bit of the first scan block having a pass value and the tag bit of the second scan block from each preceding scan block group in the scan chain having a pass value. |
地址 |
Milpitas CA US |