AUTOMATING SYSTEM ON A CHIP CUSTOMIZED DESIGN INTEGRATION, SPECIFICATION, AND VERIFICATION THROUGH A SINGLE, INTEGRATED SERVICE

摘要

A user specified high level design selects a plurality of IP cores for placement in a customized system on a chip. A single integrated service automatically performs each of a design integration phase, specification phase, and verification phase for the user specified high level design to generate an integration file specifying stitching between a plurality of pins of each of the plurality of IP cores, a specification file specifying one or more characteristics of the customized system on a chip based on the user specified high level design, and a verification testbench for verification of the user specified high level design.

主权项

1. A method, comprising:
a computer system receiving, by a single integrated service, a user specified high level design selecting a plurality of IP cores for placement in a customized system on chip; the computer system automatically performing, by the single integrated service, each of a design integration phase, specification phase, and verification phase for the user specified high level design to generate an integration file specifying stitching between a plurality of pins of each of the plurality of IP cores, a specification file specifying one or more characteristics of the customized system on a chip based on the user specified high level design, and a verification testbench for verification of the plurality of IP cores selected in the user specified high level design; the computer system performing the integration phase by identifying, for each of the plurality of IP cores, a separate IP core component and at least one separate port; the computer system creating, for each separate IP core component, a separate real IP core component in a register transfer level design; the computer system identifying, for each at least one separate port, the plurality of pins each connected to the at least one separate port; the computer system mapping each pin of the plurality of pins into a separate real pin of a plurality of real pins within one of the separate real IP core component in the register transfer level design; the computer system identifying a selection of at least two real pins from among the plurality of design pins with a same property based on a separate property setting for each of the plurality of pins specified in in a core wrappers database accessible to the single integrated service; the computer system selecting a separate connection of a plurality of connections between the selection of the at least one real pins with the same property to connect the plurality of IP cores; the computer system mapping each separate connection into the register transfer level design; and the computer system generating the integration file with the register transfer level design specifying the stitching between the plurality of pins of each of the plurality of IP cores.