Fast programming memory device

摘要

In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line, and wherein said memory cells are adapted to be programmed into at least a first programming state and a second programming state, a method of storing data comprising exploiting a single memory cell for each of the memory cells string for writing the data, wherein said exploiting includes bringing the single memory cell to the second programming state, the remaining memory cells of the string being left in the first programming state.

主权项

1. A memory device comprising:
a command interface to receive a command associated with a power down event; non-volatile memory cells coupled to the command interface; and a control circuit operable to perform a fast program operation in response to the command in order to store data in the non-volatile memory cells, wherein the control circuit is operable to perform the fast programming operation in a shorter time compared with a normal programming operation.