发明名称 Masking circuit and time-to-digital converter comprising the same
摘要 A circuit includes a reset circuit, a counter and a comparator. The reset circuit generates a reset signal based on a reference signal and a controlled signal. The reference signal and the controlled signal are to be sent to the TDC for detection of phase difference. The counter counts to a predetermined value associated with the reference signal and the controlled signal, and is reset to an initial value in response to the reset signal. The comparator compares a count from the counter and the predetermined value, and generates a mask signal when a count from the counter equals the predetermined value. The mask signal masks a portion of pulses of the controlled signal from entering the TDC.
申请公布号 US9632486(B2) 申请公布日期 2017.04.25
申请号 US201615014905 申请日期 2016.02.03
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. 发明人 Tsai Tsung-Hsien
分类号 G04F10/00;H03L7/085 主分类号 G04F10/00
代理机构 WPAT, P.C., Intellectual Property Attorneys 代理人 WPAT, P.C., Intellectual Property Attorneys ;King Anthony
主权项 1. A masking circuit for a time-to-digital converter (TDC), the masking circuit comprising: a reset circuit configured to generate a reset signal based on a reference signal and a controlled signal, the reference signal and the controlled signal to be sent to the TDC for detection of phase difference; a counter configured to count to a predetermined value associated with the reference signal and the controlled signal, and configured to be reset to an initial value in response to the reset signal; and a comparator configured to compare a count from the counter and the predetermined value, and to generate a masking signal when a count from the counter equals the predetermined value, the masking signal masking a portion of pulses of the controlled signal from entering the TDC.
地址 Hsinchu TW