发明名称 |
Enhanced wafer test line structure |
摘要 |
A semiconductor wafer has a die area and a scribe area. A first dummy pad is formed in a first test line area of the scribe area and filled with a first material as part of a first metal layer. A first interlayer dielectric is formed over the first metal layer. A first interconnect pattern is formed in the die area and above the first interlayer dielectric, and a first trench pattern is formed in the first test line area of the scribe area and above the interlayer dielectric. The first interconnect pattern and the first trench pattern are filled with a second metal layer, and the first trench pattern is aligned above the first dummy pad. An enhanced test line structure including the first trench pattern and the first dummy pad is formed and probed in a back end of line (BEOL) process.
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申请公布号 |
US8476629(B2) |
申请公布日期 |
2013.07.02 |
申请号 |
US201113246536 |
申请日期 |
2011.09.27 |
申请人 |
HUANG JIUN-JIE;LIN CHI-YEN;WANG LING-SUNG;TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
HUANG JIUN-JIE;LIN CHI-YEN;WANG LING-SUNG |
分类号 |
H01L29/788;H01L27/12 |
主分类号 |
H01L29/788 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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