发明名称 |
Expedited servicing of store operations in a data processing system |
摘要 |
In at least some embodiments, a processor core generates a store operation by executing a store instruction in an instruction sequence. The store operation is marked as a high priority store operation in response to detecting a barrier instruction in the instruction sequence immediately preceding the store instruction in program order and is not so marked otherwise. The store operation is buffered in a store queue associated with a cache memory of the processor core. Handling of the store operation in the store queue is expedited in response to the store operation being marked as a high priority store operation and not expedited otherwise. |
申请公布号 |
US9632942(B2) |
申请公布日期 |
2017.04.25 |
申请号 |
US201514839264 |
申请日期 |
2015.08.28 |
申请人 |
International Business Machines Corporation |
发明人 |
Guthrie Guy L.;Shen Hugh;Stuecheli Jeffrey A.;Williams Derek E. |
分类号 |
G06F12/00;G06F12/0875;G06F9/30;G06F3/06 |
主分类号 |
G06F12/00 |
代理机构 |
|
代理人 |
Russell Brian F.;Bennett Steven L. |
主权项 |
1. A processing unit, comprising:
a processor core including: an instruction sequencing unit that orders instructions for execution; and an execution unit that generates a store operation by executing a store instruction in an instruction sequence; a cache memory including a cache array and a store queue for buffering store operations to be serviced with respect to the cache array; and marking logic located within at least one of the processor core or the cache memory, wherein the marking logic selectively marks the store operation as a high priority store operation, wherein the marking logic marks the store operation as a high priority store operation in response to detecting a barrier instruction in the instruction sequence immediately preceding the store instruction in program order and refrains from marking the store operation as a high priority store operation in response to not detecting a barrier instruction in the instruction sequence immediately preceding the store instruction in program order; wherein the cache memory expedites handling of the store operation in the store queue in response to the store operation being marked as a high priority store operation and otherwise refrains from expediting handling of the store operation in the store queue; wherein the barrier instruction is an instruction that guarantees completion of all store operations preceding the barrier instruction prior to completing any store operations following the barrier instruction. |
地址 |
Armonk NY US |