COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR AND METHOD THEREOF

摘要

This invention application provides a complementary metal-oxide-semiconductor field-effect transistor and method thereof. The transistor comprises a semiconductor substrate, a N-type field-effect transistor positioned in the semiconductor substrate, and a P-type field-effect transistor positioned in the semiconductor substrate and spaced apart the N-type field-effect transistor. N-type field-effect transistor includes a first germanium nanowire, a first III-V compound layer surrounding around the first germanium nanowire, a first potential barrier layer mounted on the first III-V compound layer, a first gate dielectric layer, a first gate, a first source region and a first drain region mounted on two sides of the first gate. P-type field-effect transistor includes a second germanium nanowire, a second III-V compound layer surrounding around the second germanium nanowire, a second potential barrier layer mounted on the second III-V compound layer, a second gate dielectric layer, a second gate, a second source region and a second drain region mounted on two sides of the second gate. The field-effect transistor can produce two-dimensional electron gases and two-dimensional electron hole gases, and the P-type and N-type field-effect transistors are gate-surrounding devices to enhance the carrier mobility of the complementary metal-oxide-semiconductor field-effect transistor.

主权项

1. A complementary metal-oxide-semiconductor field-effect transistor comprising:
a semiconductor substrate; a N type field effect transistor disposed in the semiconductor substrate, the N type filed effect transistor including a first germanium nanowire, a first III-V compound layer surrounding around the first germanium nanowire, a first potential barrier layer disposed on the first III-V compound layer, a first gate dielectric layer, a first gate, a first source region disposed at one side of the first gate, and a first drain region disposed at an opposite side of the first gate; and a P type field effect transistor disposed in the semiconductor substrate, another dielectric layer disposed between the N type and P type filed effect transistors, the P type filed effect transistor including a second germanium nanowire, a second III-V compound layer surrounding around the second germanium nanowire, a second potential barrier layer disposed on the second III-V compound layer, a second gate dielectric layer, a second gate, a second source region disposed at one side of the second gate, and a second drain region disposed at an opposite side of the second gate.