发明名称 SELECTIVE BOTTOM-UP METAL FEATURE FILLING FOR INTERCONNECTS
摘要 A method for selective bottom-up filling of recessed features with a low resistivity metal for semiconductor devices is described in several embodiments. The method includes providing a substrate containing a patterned dielectric layer having a recessed feature with dielectric layer surfaces and a metal-containing surface on a bottom of the recessed feature, reacting the dielectric layer surfaces with a reactant gas containing a hydrophobic functional group to form hydrophobic dielectric layer surfaces, and at least substantially filling the recessed feature with a metal in a bottom-up gas phase deposition process that hinders deposition of the metal on the hydrophobic dielectric layer surfaces. According to one embodiment, the metal is selected from the group consisting of ruthenium (Ru), cobalt (Co), aluminum (Al), iridium (Ir), iridium (Ir), rhodium (Rh), osmium (Os), palladium (Pd), platinum (Pt), nickel (Ni), and a combination thereof.
申请公布号 US2017110368(A1) 申请公布日期 2017.04.20
申请号 US201615293902 申请日期 2016.10.14
申请人 Tokyo Electron Limited 发明人 Yu Kai-Hung;Tapily Kandabara N.;Clark Robert D.;Leusink Gerrit J.
分类号 H01L21/768;H01L23/522;H01L23/528;H01L23/532 主分类号 H01L21/768
代理机构 代理人
主权项 1. A method of forming a semiconductor device, the method comprising: providing a substrate containing a patterned dielectric layer having a recessed feature with dielectric layer surfaces and a metal-containing surface on a bottom of the recessed feature; reacting the dielectric layer surfaces with a reactant gas containing a hydrophobic functional group to form hydrophobic dielectric layer surfaces; and at least substantially filling the recessed feature with a metal in a bottom-up gas phase deposition process that hinders deposition of the metal on the hydrophobic dielectric layer surfaces.
地址 Tokyo JP