BUFFER CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT, AND SYSTEM INCLUDING THE BUFFER CIRCUIT

摘要

According to an embodiment, a buffer circuit may be provided. The buffer circuit may include a first buffer configured to receive first and second external clock signals and generate a first pre-clock signal based on falling timings of the first and second external clock signals. The buffer circuit may include a second buffer configured to receive the first and second external clock signals and generate a second pre-clock signal based on raising timings of the first and second external clock signals.

主权项

1. A buffer circuit comprising:
a first buffer configured to generate a first pre-clock signal based on a first external clock signal and a second external clock signal; a second buffer configured to generate a second pre-clock signal based on the first external clock signal and the second external clock signal; a delay control block configured to generate a plurality of delay control signals based on the first and second pre-clock signals; a first delay configured to determine a delay time in response to the plurality of delay control signals, delay the first pre-clock signal by the determined delay time, and output a first internal clock signal; and a second delay configured to determine a delay time based on the plurality of delay control signals, delay the second pre-clock signal by the determined delay time, and output a second internal clock signal.