Spur reduction in phase locked loops using reference clock dithering

摘要

An embodiment of the present disclosure provides a phase locked loop. A controllable oscillator generates a radio frequency (RF) signal. A divider is configured to produce a divided RF signal by dividing the RF signal by a division factor. A phase detection circuit is configured to receive a dithered reference signal and the divided RF signal and to produce a phase error signal for controlling the oscillator. A dithering module is configured produce the dithered reference signal and the division factor, in which the dithered reference signal has a randomly changing frequency selected from a plurality of dither frequencies, and in which the division factor is synchronously selected to match a ratio between each selected dither frequency and a target frequency of the RF signal.

主权项

1. A digital system comprising a phase locked loop (PLL), wherein the PLL comprises:
a controllable oscillator for generating a radio frequency (RF) signal having a target frequency; a divider coupled to receive the RF signal, the divider configured to produce a divided RF signal by dividing the RF signal by a division factor; a phase detection circuit configured to receive a dithered reference signal and the divided RF signal and to produce a phase error signal for controlling the oscillator; and a dithering module configured to receive a reference signal having a fixed frequency FREF, the dithering module operable to produce the dithered reference signal and the division factor, in which the dithered reference signal has a randomly changing frequency selected from a plurality of dither frequencies, and in which the division factor is synchronously selected to match a ratio between each selected dither frequency and the target frequency of the RF signal.