Non volatile memory cell and memory array

摘要

A non-volatile memory cell for storing a single bit is disclosed. The non-volatile memory cell includes an access transistor including a gate, a first body, a first source/drain node, and a second source/drain node. The non-volatile memory cell also includes a first floating gate storage transistor that has a third source/drain node, a second body, a fourth source/drain node, and a first floating gate including a first storage node. The third source/drain node is coupled to the second source/drain node. The non-volatile memory cell further includes a first capacitor, a second capacitor, and a second floating gate storage transistor. The first capacitor has a first plate coupled to the first storage node and an opposite second plate. The second floating gate storage transistor includes a fifth source/drain node, a third body, a sixth source/drain node, a second floating gate including a second storage node. The fifth source/drain node is coupled to the fourth source/drain node. The second capacitor includes a third plate coupled to the second storage node and having an opposite fourth plate. The second plate is coupled to the fourth plate, and the first body of the access transistor is coupled to the second body and the third body.

主权项

1. A non-volatile memory cell for storing a single bit, the non-volatile memory cell comprising:
an access transistor comprising a gate, a first body, a first source/drain node, and a second source/drain node; a first floating gate storage transistor comprising a third source/drain node, a second body, a fourth source/drain node, and a first floating gate comprising a first storage node, wherein the third source/drain node is coupled to the second source/drain node; a first capacitor comprising a first plate coupled to the first storage node and having an opposite second plate; a second floating gate storage transistor comprising a fifth source/drain node, a third body, a sixth source/drain node, a second floating gate comprising a second storage node, wherein the fifth source/drain node is coupled to the fourth source/drain node; and a second capacitor comprising a third plate coupled to the second storage node and having an opposite fourth plate, wherein the second plate is coupled to the fourth plate, wherein the first body of the access transistor is coupled to the second body and the third body.