Semiconductor device having gate structures and manufacturing method thereof

摘要

A semiconductor device includes a substrate having a first conductivity type, a high-voltage well having a second conductivity type and disposed in the substrate, a high-voltage doped region having the first conductivity type and disposed in the high-voltage well, a drain region disposed in the high-voltage well and spaced apart from the high-voltage doped region, a source region disposed in the high-voltage doped region, a first gate structure disposed above a first side portion of the high-voltage doped region between the source region and the drain region, and a second gate structure disposed above a second and opposite side portion of the high-voltage doped region.

主权项

1. A semiconductor device, comprising:
a substrate having a first conductivity type; a high-voltage well having a second conductivity type and disposed in the substrate; a high-voltage doped region having the first conductivity type and disposed in the high-voltage well; a drain region disposed in the high-voltage well and spaced apart from the high-voltage doped region; a source region disposed in the high-voltage doped region; a first gate structure disposed above a first side portion of the high-voltage doped region between the source region and the drain region; and a second gate structure disposed above a second and opposite side portion of the high-voltage doped region; wherein the first gate structure includes a first gate layer and a first gate oxide layer, and the second gate structure includes a second gate layer and a second gate oxide layer, the first gate structure including the first gate oxide layer covers an edge portion of a first field oxide portion that overlaps the first side portion of the high-voltage doped region between the source region and the drain region, the second gate structure including the second gate oxide layer covers an edge portion of a second field oxide portion that overlaps the second and opposite side portion of the high-voltage doped region, and the thickness of the first gate oxide layer being greater than the thickness of the second gate oxide layer.