发明名称 |
Latch circuit, receiver circuit, semiconductor apparatus and system using the latch and receiver circuits |
摘要 |
A latch circuit, a receiver circuit, a semiconductor apparatus, or a system may be provided. The latch circuit may include a delay configured to delay an input signal and generate a delay signal. The latch circuit may include a control signal generator configured to enable a control signal based on the input signal and the delay signal, and disable the control signal based on a reset signal. The latch circuit may include a gating circuit configured to output, based on the control signal, the input signal and the delay signal to an output node. The latch circuit may include a latch configured to latch, based on a strobe pulse, an output of the gating circuit and generate an output signal. |
申请公布号 |
US9628056(B1) |
申请公布日期 |
2017.04.18 |
申请号 |
US201615163219 |
申请日期 |
2016.05.24 |
申请人 |
SK HYNIX INC. |
发明人 |
Lee Wan Seob |
分类号 |
H03K3/00;H03K3/356;H03K5/13;G11C7/10;H03K5/00 |
主分类号 |
H03K3/00 |
代理机构 |
William Park & Associates Ltd. |
代理人 |
William Park & Associates Ltd. |
主权项 |
1. A latch circuit comprising:
a delay configured to delay an input signal and generate a delay signal; a control signal generator configured to enable a control signal based on the input signal and the delay signal, and disable the control signal based on a reset signal; a gating circuit configured to output, based on the control signal, the input signal and the delay signal to an output node; and a latch configured to latch, based on a strobe pulse, an output of the gating circuit and generate an output signal. |
地址 |
Icheon-si KR |