Twin memory cell interconnection structure

摘要

Non-volatile memory including rows and columns of memory cells, the columns of memory cells including pairs of twin memory cells including a common selection gate. According to the disclosure, two bitlines are provided per column of memory cells. The adjacent twin memory cells of the same column are not connected to the same bitline while the adjacent non-twin memory cells of the same column are connected to the same bitline.

主权项

1. A non-volatile memory, comprising:
a first twin pair of memory cells, the first twin pair including first and second memory cells arranged in a first column, the first and second memory cells each including a respective selection transistor and a respective floating gate transistor, the selection transistors of the first twin pair having respective gate terminals coupled to one another; a second twin pair of memory cells, the second twin pair including third and fourth memory cells arranged in the first column, the third memory cell being adjacent to the second memory cell, the third and fourth memory cells each including a respective selection transistor and a respective floating gate transistor, the selection transistors of the second twin pair having respective gate terminals coupled to one another; a first bitline coupled to conduction terminals of the floating gate transistors of the first and fourth memory cells; a second bitline coupled to conduction terminals of the floating gate transistors of the second and third memory cells; a first word line coupled to the gate terminals of the selection transistors of the first twin pair; and a second word line coupled to the gate terminals of the selection transistors of the second twin pair.