发明名称 THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE
摘要 A semiconductor device includes lower and upper selection lines, a cell gate structure, a lower dummy structure and an upper dummy structure. The cell gate structure is between the lower and upper selection lines and includes cell gate electrodes stacked in a first direction. The lower dummy structure is between the lower selection line and the cell gate structure and includes a lower dummy gate line spaced from a lowermost one of the cell gate electrodes by a first distance. The upper dummy structure is between the upper selection line and the cell gate structure and includes an upper dummy gate line spaced from an uppermost one of the cell gate electrodes by a second distance. The cell gate electrodes are spaced by a third distance less than each of the first and second distances.
申请公布号 US2017103999(A1) 申请公布日期 2017.04.13
申请号 US201615291521 申请日期 2016.10.12
申请人 Samsung Electronics Co., Ltd. 发明人 LEE Jung Hoon;RHO Keejeong;PARK Sejun;SHIN Jinhyun;LEE Dong-Sik;LEE Woong-Seop
分类号 H01L27/115;H01L23/528 主分类号 H01L27/115
代理机构 代理人
主权项 1. A three-dimensional (3D) semiconductor memory device, comprising: a lower selection line and at least one upper selection line stacked on a substrate in a first direction crossing to a top surface of the substrate; a cell gate structure between the lower selection line and the at least one upper selection line, the cell gate structure including cell gate electrodes stacked in the first direction; a lower dummy structure between the lower selection line and the cell gate structure, the lower dummy structure including a lower dummy gate line spaced apart from a lowermost one of the cell gate electrodes in the first direction by a first distance; and an upper dummy structure between the at least one upper selection line and the cell gate structure, the upper dummy structure including an upper dummy gate line spaced apart from an uppermost one of the cell gate electrodes in the first direction by a second distance, wherein the lower dummy gate line and the upper dummy gate line are immediately adjacent to the lowermost cell gate electrode and the uppermost cell gate electrode, respectively, wherein the cell gate electrodes are spaced apart from each other in the first direction by a third distance, and wherein each of the first and second distances is greater than the third distance.
地址 Suwon-Si, Gyeonggi-do KR