Reconfigurable semiconductor integrated circuit and electronic device

摘要

According to an embodiment, a reconfigurable semiconductor integrated circuit includes first and second blocks. The first block includes first memories; and second memories; a selector selecting one first memory and one second memory; a first logic circuit whose logic is determined according to data read from the selected first memory; and a first switch circuit that is connected to first wires and switches connection between the first wires according to data read from the selected second memory, a part of the first wires being connected to the first logic circuit. The second block includes third and fourth memories; a second logic circuit whose logic is determined according to data read from the third memory; and a second switch circuit that is connected to second wires and switches connection between the second wires according to data read from the fourth memory, a part of the second wires being connected to the second logic circuit.

主权项

1. A reconfigurable semiconductor integrated circuit comprising a first block and a second block, wherein
the first block includes:
first memories that store therein a plurality of values;second memories that store therein a plurality of values;a first logic circuit whose logic is determined according to data selected with a selection signal from the first memories; anda first switch circuit that is connected to first wires through which data are transmitted and switches connection between the first wires according to data read from the memory selected by the selector from the second memories, a part of the first wires being connected to the first logic circuit, and the second block includes:
a third memory that stores therein a single value;a fourth memory that stores therein a single value;a second logic circuit whose logic is determined according to data read from the third memory; anda second switch circuit that is connected to second wires through which data are transmitted and switches connection between the second wires according to data read from the fourth memory, a part of the second wires being connected to the second logic circuit.