AREA AWARE SCHEMATIC DESIGN BY ANALYSING AREA OF EACH COMPONENT USING SCRIPTING LANGUAGES

摘要

An area aware schematic design system that analyses an area of one or more components in a schematic circuit using scripting tools to generate an optimised component placement layout design for designing the schematic circuit is provided. The area aware schematic design system includes one or more modules as follows. A schematic circuit design module designs a schematic circuit. A schematic netlist analysing module performs an analysis on the schematic circuit. A component area parameter module calculates an area of the one or more components. A component information updation module obtains a second set of component information. A circuit design optimisation module design and optimise the schematic circuit design based on the second set component information. A component placement layout module generates an optimized component placement layout design. A layout closure module delivers the optimised component placement layout design.

主权项

1. An area aware schematic design system that analyses an area of a plurality of components in a schematic circuit using scripting tools to generate an optimised component placement layout design for designing said schematic circuit, said system comprising:
(a) a memory unit that stores a database, and a set of modules; and (b) a processor that executes said set of modules, wherein said set of modules comprises:
a schematic circuit design module, implemented by said processor, that designs said schematic circuit comprising said plurality of components to be compatible with circuit specifications of said plurality of components based on a first set of component information that comprises a first width of said plurality of components, a first length of said plurality of components, at least one finger of said plurality of components, and at least one multiplier of said plurality of components;a component area parameter module, implemented by said processor, that calculates an area of (a) at least one component of said plurality of components, (b) at least one component type of said plurality of components, and (c) at least one group of components of said plurality of components;a component information updation module, implemented by said processor, that obtains a second set of component information comprising a second length of said plurality of components, a second width of said plurality of components, at least one finger of said plurality of components, and at least one multiplier of said plurality of components, wherein said second set of component information is optimised for area based on area parameters comprising said area of said (a) at least one component of said plurality of components, (b) at least one component type of said plurality of components, and (c) at least one group of components of said plurality of components;a circuit design optimisation module, implemented by said processor, that design and optimise a schematic circuit design based on said second set component information that is optimised for area based on said area parameters;a component placement layout module, implemented by said processor, that generates an optimised component placement layout design based on said second set of component information that is optimised for area based on said area parameters; anda layout closure module, implemented by said processor, that delivers said optimised component placement layout design as a final output for generating an optimized circuit.