Transmitter Architecture for Photoplethysmography Systems

摘要

An LED (light-emitting diode) driver for a photoplethysmography system, including a switched-mode operational amplifier for driving a driver transistor with a source-drain path in series with the LED. In a first clock phase in which the LED is disconnected from the driver transistor, the amplifier is coupled in unity gain mode, and a sampling capacitor stores a voltage corresponding to the offset and flicker noise of the amplifier; the gate of the driver transistor is precharged to a reference voltage in this first clock phase. In a second clock phase, the sampled voltage at the capacitor is subtracted from the reference voltage applied to the amplifier input, so that the LED drive is adjusted according to the sampled noise. A signal from the transmitter channel is forwarded to a noise/ripple remover in the receiving channel, to remove transmitter noise from the received signal.

主权项

1. A driver circuit for a light-emitting diode (LED), comprising;
a driver transistor having a source, drain, and gate, the source-drain path of the driver transistor coupled in series with the LED between a power supply voltage and a ground node; a first switch coupled between the LED and the source-drain path of the driver transistor; an amplifier, having non-inverting and inverting inputs, and having an output coupled to the gate of the driver transistor; a first capacitor having a first plate at a sample node and a second plate connected to the non-inverting input of the amplifier; a second switch connected between the source of the driver transistor and the inverting input of the amplifier; a third switch connected between a reference voltage input and the sample node; a fourth switch connected between a reference voltage input and the non-inverting input of the amplifier; a fifth switch connected between the output of the amplifier and the sample node; a sixth switch connected between the output of the amplifier and the sample node; and timing control circuitry for generating first and second clock phases; wherein the fourth, fifth, and sixth switches are coupled to receive the first clock phase, and are closed during the first clock phase; and wherein the fourth, fifth, and sixth switches are coupled to receive the first clock phase, and are closed during the first clock phase.