发明名称 |
Higher accuracy Z-culling in a tile-based architecture |
摘要 |
A graphics processing pipeline configured for z-cull operations. The graphics processing pipeline comprising a screen-space pipeline and a tiling unit. The screen-space pipeline includes a z-cull unit configured to perform z-culling operations. The tiling unit is configured to determine that a first set of primitives overlaps a first cache tile. The tiling unit is also configured to transmit the first set of primitives to the screen-space pipeline for processing. The tiling unit is further configured to select between processing the first set of primitives in a full-surface z-cull mode or processing the first set of primitives in a partial-surface z-cull mode. The tiling unit is also configured to cause the z-cull unit to process the first set of primitives in the full-surface z-cull mode or to process the first set of primitives in the partial-surface z-cull mode. |
申请公布号 |
US9612839(B2) |
申请公布日期 |
2017.04.04 |
申请号 |
US201314061443 |
申请日期 |
2013.10.23 |
申请人 |
NVIDIA Corporation |
发明人 |
Hakura Ziyad S.;Duluk, Jr. Jerome F. |
分类号 |
G06F9/38;G06T15/00;G06T15/40;G06T1/20;G06T1/60;G09G5/395;G09G5/00;G06T15/50;G06F12/0808;G06F12/0875;G06F9/44;G06T15/80 |
主分类号 |
G06F9/38 |
代理机构 |
Artegis Law Group, LLP |
代理人 |
Artegis Law Group, LLP |
主权项 |
1. A tile-based graphics processing pipeline configured for z-culling operations, the graphics processing pipeline comprising:
a screen-space pipeline that includes a z-cull processor configured to perform z-culling operations; a tiling processor configured to:
determine that a first set of primitives overlaps a first cache tile, transmit the first set of primitives to the screen-space pipeline for processing,select between processing the first set of primitives in a full-surface z-cull mode or processing the first set of primitives in a partial-surface z-cull mode, wherein, in the partial-surface z-cull mode, the first cache tile is divided into a plurality of sub-cache-tile areas, andin response to selecting between processing the first set of primitives in a full-surface z-cull mode or processing the first set of primitives in a partial-surface z-cull mode, cause the z-cull processor to process the first set of primitives in the full-surface z-cull mode or to process the first set of primitives in the partial-surface z-cull mode; and a z-cull memory configured to store first z-cull data in the full-surface z-cull mode and to store second z-cull data in the partial-surface z-cull mode. |
地址 |
Santa Clara CA US |