Phase locked loop with lock detector

摘要

A phase locked loop is disclosed comprising: a phase detector, loop filter and a frequency controlled oscillator. The phase detector is configured to determine a phase difference between a reference signal and a feedback signal. The loop filter is configured to perform a filtering operation on a signal derived from the phase difference and to provide a control signal. The frequency controlled oscillator is configured to receive the control signal and provide an output signal with a frequency that varies according to the control signal. The phase locked loop further comprises a lock detector, including: a phase lock detector configured to receive a first signal from the phase locked loop, and to derive a phase lock signal from the first signal; a frequency lock detector configured to receive a second signal from the phase locked loop, and to derive a frequency lock signal from the second signal. An unlock detector may be provided, configured to determine whether the first signal has changed by a predetermined amount during a predetermined period.

主权项

1. A phase locked loop comprising:
a phase detector configured to determine a phase difference between a reference signal and a feedback signal; a loop filter configured to perform a filtering operation on a signal derived from the phase difference and to provide a control signal; a frequency controlled oscillator configured to receive the control signal and provide an output signal with a frequency that varies according to the control signal; and a lock detector, including:
a phase lock detector including a first comparator coupled to a first timer, wherein the first timer is configured to receive a first comparator output from the first comparator, wherein the phase lock detector is configured to receive a first signal from the phase locked loop, and to derive a phase lock signal from the first signal, the phase lock signal indicating whether the phase locked loop is in phase lock;a frequency lock detector configured to receive a second signal from the phase locked loop, and to derive a frequency lock signal from the second signal, the frequency lock signal indicating whether the phase locked loop is in frequency lock.