Multiple-time programmable memory

摘要

A multiple-time programmable (MTP) structure is provided that can operate using a power supply with a supply voltage of 1.5 V to 5.5 V. When the supply voltage is above a first voltage, a first circuit is configured to induce a second constant voltage at a drain of a second transistor, and to induce the second constant voltage on a terminal in a third circuit. In some embodiments, the third circuit provides a third constant voltage on a gate of a third transistor. When the supply voltage is below the first voltage, a fifth circuit is configured to induce a fourth constant voltage on a terminal in the third circuit. The fourth constant voltage is substantially equal to the second constant voltage.

主权项

1. A method, comprising:
during a read operation:
activating a first transistor having a first source/drain region coupled to a digital-output node;activating a floating gate transistor having a gate coupled to a word line, a first source/drain region coupled to a voltage source, and a second source/drain region coupled to the digital-output node,
wherein the digital-output node is pulled to a first voltage while the first transistor and the floating gate transistor are activated; anddeactivating the first transistor while the floating gate transistor remains activated,
wherein the digital-output node is pulled to a second voltage while the first transistor is deactivated and the floating gate transistor is activated when the floating gate transistor is in a first logic state, andwherein the digital-output node is pulled to a third voltage while the first transistor is deactivated and the floating gate transistor is activated when the floating gate transistor is in a second logic state.