Testing memory devices with parallel processing operations

摘要

An ATE system performs RA over NAND flash memory DUTs. A first UBM captures fresh failure related data from a DUT. A second UBM transmits existing failure related data. A fail engine accesses the stored existing failure related data and generates a failure list based thereon. The storing and the accessing the existing failure related data, and/or the generating the failure list, are performed in parallel contemporaneously in relation to the capturing the fresh data. The generated failure list is queued. A failure processor, which may be operable for controlling the capturing, computes a redundancy analysis based on the queued failure list. The first and second UBMs then ping-pong operably.

主权项

1. A system for testing a device under test (DUT), the system comprising:
a first buffer memory bank operable for capturing fresh failure related data from the device under test at a first time; a second buffer memory bank operable for transmitting existing failure related data from a previous DUT test, which precedes the first time; a fail engine operable for accessing the existing failure related data and for generating a failure list based thereon, wherein one or more of the receiving the existing failure related data, the accessing the existing failure related data, and the generating the failure list, is performed contemporaneously in relation to the capturing the fresh failure related data; a queue operable for queuing a generated failure list; and a failure processor operable for controlling the capturing and for computing a redundancy analysis based on a queued failure list.