Digital signal processing blocks with embedded arithmetic circuits

摘要

A specialized processing block on an integrated circuit includes a first and second arithmetic operator stage, an output coupled to another specialized processing block, and configurable interconnect circuitry which may be configured to route signals throughout the specialized processing block, including in and out of the first and second arithmetic operator stages. The configurable interconnect circuitry may further include multiplexer circuitry to route selected signals. The output of the specialized processing block that is coupled to another specialized processing block together with the configurable interconnect circuitry reduces the need to use resources outside the specialized processing block when implementing mathematical functions that require the use of more than one specialized processing block. An example for such mathematical functions include the implementation of vector (dot product) operations, FIR filters, or sum-of-product operations.

主权项

1. An integrated circuit, comprising:
first and second specialized processing blocks, wherein the first specialized processing block comprises:
a first arithmetic operator stage;a second arithmetic operator stage; andan output that is directly coupled to the second specialized processing block, wherein the first arithmetic operator stage has an output port that is coupled to the output of the first specialized processing block via a first path and that is coupled to an input port of the second arithmetic operator stage via a second path that is separate from the first path.