| 摘要 |
Embodiments include a sense amplifier circuit including first and second paths that may be selectively coupled to a memory cell or a reference cell as part of a two-phase read process. The sense amplifier may include a biasing circuit to provide an adaptive bias voltage to a transistor of the first and/or second path to cause the transistor to provide a voltage across the memory cell and/or reference cell that is substantially constant across process corners. The sense amplifier may include a DC-coupled regenerative latch circuit to generate a digital output signal based on a voltage difference between nodes of the first and second paths at or near the end of the second phase. Trimmable offset resistors may adjust a resistance value provided to the sense amplifier by the memory cell and/or reference cells. Other embodiments may be described and claimed. |
