| 发明名称 |
SEMICONDUCTOR MEMORY DEVICE AND TEST METHOD THEREFOR |
| 摘要 |
Provided is a semiconductor memory device that is capable of accurately detecting a retention failure of a memory cell. The semiconductor memory device includes a memory array including a plurality of memory cells arranged in a matrix form, a plurality of bit line pairs disposed in the columns of the memory cells, a plurality of word lines disposed in the rows of the memory cells, a write drive circuit adapted to transfer data to a bit line pair in a selected column in accordance with write data, and a control circuit that deselects the word lines during a test and drives a low-potential side bit line of the bit line pair in the selected column to a negative voltage level in accordance with the potentials of bit lines in the selected column. |
| 申请公布号 |
US2017092378(A1) |
申请公布日期 |
2017.03.30 |
| 申请号 |
US201615234910 |
申请日期 |
2016.08.11 |
| 申请人 |
Renesas Electronics Corporation |
发明人 |
TANAKA Shinji;ISHll Yuichiro;TSUKUDE Masaki;SAITO Yoshikazu |
| 分类号 |
G11C29/12;G11C11/419;G11C11/418 |
主分类号 |
G11C29/12 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A semiconductor memory device comprising:
a memory array that includes a plurality of memory cells arranged in a matrix form; a plurality of bit line pairs that are disposed in the columns of the memory cells; a plurality of word lines that are disposed in the rows of the memory cells; a write drive circuit that transfers data to a bit line pair in a selected column in accordance with write data; and a control circuit that deselects the word lines during a test and drives a low-potential side bit line of the bit line pair in the selected column to a negative voltage level in accordance with the potentials of bit lines in the selected column. |
| 地址 |
Tokyo JP |
