METHOD AND APPARATUS FOR EFFECTIVE CLOCK SCALING AT EXPOSED CACHE STALLS

摘要

The clock frequency of a processor is reduced in response to a dispatch stall due to a cache miss. In an embodiment, the processor clock frequency is reduced for a load instruction that causes a last level cache miss, provided that the load instruction is the oldest load instruction and the number of consecutive processor cycles in which there is a dispatch stall exceeds a threshold, and provided that the total number of processor cycles since the last level cache miss does not exceed some specified number.

主权项

1. A processor comprising:
a register file having a register; a pipeline, wherein upon detecting a load instruction causing a last level cache miss while there are no other outstanding load instructions in the pipeline that caused another last level cache miss, the pipeline stores in the register an identification of the load instruction and sets a field in the register to indicate the content of the register is valid; and a state machine coupled to the register file and the pipeline, wherein the state machine transitions from an initial state to a first state in response to the pipeline storing the identification in the register, the state machine transitions from the first state to a second state in response to the load instruction being the oldest load instruction in the pipeline, and the state machine transitions from the second state to a low frequency state in response to the processor operating over M contiguous processor clock cycles since the state machine transitioned to the second state, where M is an integer; wherein the processor operates at a first clock frequency when the state machine is in the initial, first, or second states, and operates at a second clock frequency when the state machine is in the low frequency state, where the first clock frequency is higher than the second clock frequency.