发明名称 | Memory system | ||
摘要 | According to one embodiment, a memory system includes a memory and a setting unit. The memory includes a memory cell array and a peripheral circuit. The memory cell array includes a plurality of memory cells, each of which holds an electrical charge. The peripheral circuit is configured to read a value from each memory cell by comparing a quantity of an electrical charge held in the memory cell with a determination threshold. The memory stores first data in the memory cell array. The first data include a plurality of values. The setting unit is configured to change the determination threshold according to the number of values which are different in second data and third data among the plurality of values. The second data are first data before being written to the memory. The third data are first data that have been read from the memory. | ||
申请公布号 | US9607703(B2) | 申请公布日期 | 2017.03.28 |
申请号 | US201514639044 | 申请日期 | 2015.03.04 |
申请人 | Kabushiki Kaisha Toshiba | 发明人 | Kanno Shinichi |
分类号 | H03M13/43;G11C16/26;H03M13/05;H03M13/00;G11C16/04;G11C11/56;G11C16/10 | 主分类号 | H03M13/43 |
代理机构 | White & Case LLP | 代理人 | White & Case LLP |
主权项 | 1. A memory system comprising: a memory that includes a memory cell array including a plurality of memory cells, each of which holds an electrical charge, and includes a peripheral circuit configured to read a value from each memory cell by comparing a quantity of an electrical charge held in the memory cell with a determination threshold, the memory storing first data in the memory cell array, the first data including a plurality of values; and a setting unit configured to count the number of values which are different in second data and third data among the plurality of values and change the determination threshold according to the number of the values, the second data being first data before being written to the memory, and the third data being first data that have been read from the memory. | ||
地址 | Tokyo JP |