发明名称 Semiconductor device
摘要 A semiconductor device which shifts a low-level signal is provided. In an example, a first transistor including a first terminal electrically connected to a first wiring and a second terminal electrically connected to a second wiring, a second transistor including a first terminal electrically connected to a third wiring and a second terminal electrically connected to the second wiring, a third transistor including a first terminal electrically connected to a fourth wiring and a second terminal electrically connected to a gate of the second transistor, a fourth transistor including a first terminal electrically connected to a fifth wiring, a second terminal electrically connected to a gate of the third transistor, and a gate electrically connected to a sixth wiring, and a first switch including a first terminal electrically connected to the third wiring and a second terminal electrically connected to a gate of the first transistor are included.
申请公布号 US9608010(B2) 申请公布日期 2017.03.28
申请号 US201514713941 申请日期 2015.05.15
申请人 Semiconductor Energy Laboratory Co., Ltd. 发明人 Umezaki Atsushi
分类号 G11C19/00;H01L27/12;G11C19/28;H01L27/088;H01L27/15;H01L27/32 主分类号 G11C19/00
代理机构 Husch Blackwell LLP 代理人 Husch Blackwell LLP
主权项 1. An electronic device comprising a first circuit comprising: a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; and a first switch, wherein one of a source and a drain of the first transistor is electrically connected with one of a source and a drain of the second transistor, wherein one of a source and a drain of the third transistor is electrically connected with a first terminal of the first switch, wherein the one of the source and the drain of the third transistor is electrically connected with a gate of the second transistor, wherein the other of the source and the drain of the third transistor is electrically connected with a first signal line, wherein one of a source and a drain of the fourth transistor is electrically connected with a gate of the first transistor, wherein a gate of the fourth transistor is electrically connected with a gate of the third transistor, wherein one of a source and a drain of the fifth transistor is electrically connected with the gate of the third transistor, and wherein the other of the source and the drain of the fifth transistor is electrically connected with a second signal line.
地址 JP