发明名称 THERMALLY-AWARE THROTTLING IN A THREE-DIMENSIONAL PROCESSOR STACK
摘要 A three-dimensional (3-D) processor stack includes a plurality of processor cores implemented in a plurality of layers. A controller is to selectively throttle one or more of a plurality of processor cores in response to detecting a thermal event. The controller selectively throttles the one or more of the plurality of processor cores based on values of thermal couplings between the plurality of layers and based on measures of criticality of threads executing on the plurality of processor cores.
申请公布号 US2017083065(A1) 申请公布日期 2017.03.23
申请号 US201514862044 申请日期 2015.09.22
申请人 Advanced Micro Devices, Inc. 发明人 Huang Wei;Arora Manish;Eckert Yasuko;Paul Indrani
分类号 G06F1/20;G06F1/32;G06T1/20 主分类号 G06F1/20
代理机构 代理人
主权项 1. A method comprising: generating values of thermal couplings between a plurality of layers of a three-dimensional processor stack that includes a plurality of processor cores, wherein at least one of the plurality of processor cores is implemented in each of the plurality of layers, and wherein the values of the thermal couplings indicate temperature changes in each of the plurality of layers as a function of temperature changes in each of the other layers; and in response to a thermal event in one of the plurality of layers, selectively throttling at least one of the plurality of processor cores implemented in the plurality of layers based on the values of the thermal couplings and measures of criticality of threads executing on the plurality of processor cores.
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