| 发明名称 |
MEMORY DEVICE WITH FLEXIBLE DATA TRANSFER RATE INTERFACE AND METHOD THEREOF |
| 摘要 |
A memory device includes an input/output interface configured to receive and output signals. The input/output interface is configured to receive a memory address to be accessed and data sequence information within a clock cycle or at a rising or falling edge of a clock cycle. The data sequence information specifies an input or output data sequence. |
| 申请公布号 |
US2017083439(A1) |
申请公布日期 |
2017.03.23 |
| 申请号 |
US201514860744 |
申请日期 |
2015.09.22 |
| 申请人 |
Macronix International Co., Ltd. |
发明人 |
CHANG Kuen-Long;LO Su-Chuch;LIN Chao Hsin;CHEN Ken-Hui |
| 分类号 |
G06F12/06 |
主分类号 |
G06F12/06 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A memory device comprising:
an input/output interface configured to receive and output signals, wherein the input/output interface is configured to receive a memory address to be accessed and data sequence information within a clock cycle or at a rising or falling edge of a clock cycle, the data sequence information specifying an input or output data sequence. |
| 地址 |
Hsinchu TW |
