On-chip Atomic Transaction Engine

摘要

A hardware-assisted Distributed Memory System may include software configurable shared memory regions in the local memory of each of multiple processor cores. Accesses to these shared memory regions may be made through a network of on-chip atomic transaction engine (ATE) instances, one per core, over a private interconnect matrix that connects them together. For example, each ATE instance may issue Remote Procedure Calls (RPCs), with or without responses, to an ATE instance associated with a remote processor core in order to perform operations that target memory locations controlled by the remote processor core. Each ATE instance may process RPCs (atomically) that are received from other ATE instances or that are generated locally. For some operation types, an ATE instance may execute the operations identified in the RPCs itself using dedicated hardware. For other operation types, the ATE instance may interrupt its local processor core to perform the operations.

主权项

1. A method, comprising:
performing by a plurality of processor cores, each of which is associated with a respective atomic transaction engine instance:
beginning execution of a distributed application;determining, during execution of a portion of the distributed application on one of the plurality of processor cores, that an operation of the distributed application that targets a location in a distributed shared memory is to be performed using a remote procedure call (RPC);generating, by the atomic transaction engine instance associated with the one of the plurality of processor cores, an RPC request frame, wherein the RPC request frame comprises a descriptor and an identifier of the targeted location in the distributed shared memory, and wherein the descriptor comprises an identifier of the operation's type;providing the RPC request frame to the atomic transaction engine instance associated with another one of the plurality of processor cores;wherein each of the plurality of processor cores controls a respective portion of the distributed shared memory; andwherein the other one of the plurality of processor cores controls the portion of the distributed shared memory comprising the targeted location in the distributed shared memory.