METHOD FOR EXPOSING POLYSILICON GATES

摘要

A method for exposing polysilicon gate electrodes is disclose. The method comprises planarizing a pre-metal dielectric on a wafer surface; performing a selective etching process to the planarized pre-metal dielectric and a multi-layer dielectric which covers polysilicon gates in the wafer according to pre-set etching parameters to expose the polysilicon gates in the wafer. The selective etching process effectively control the amount of etching, which ensures high surface flatness when exposing the polysilicon gates without affecting the subsequent film deposition process. Therefore, wafer surface defects, gate stack damages, and polysilicon gate deformation caused by the conventional CMP process or the shear stress generated during the CMP process can be avoided, and then product yield can be enhanced.

主权项

1. A method for exposing polysilicon gate electrodes comprises:
providing a wafer on which a multi-layer dielectric and a pre-metal dielectric are formed from bottom to top, wherein polysilicon gates are formed in the wafer and covered by the multi-layer dielectric; planarizing the pre-metal dielectric; performing a selective etching process to the planarized pre-metal dielectric and the multi-layer dielectric according to pre-set etching parameters to expose the polysilicon gates.