CONFIGURABLE AND SCALABLE BUS INTERCONNECT FOR MULTI-CORE, MULTI-THREADED WIRELESS BASEBAND MODEM ARCHITECTURE

摘要

Various aspects of this disclosure describe a bi-directional, dual interconnect bus configured in a ring to route data to processors implementing modem functions. A plurality of nodes may be coupled to form a ring bus comprising at least two interconnect rings. A plurality of processors may be assigned to the plurality of nodes. A first processor among the plurality of processors may be configured to process a first data type, and a second processor among the plurality of processors may be configured to process a second data type. Data on the ring bus may be separated into the first data type and the second data type, and separated data of the first data type may be routed on one interconnect ring to the first processor and separated data of the second data type may be routed on another interconnect ring to the second processor.

主权项

1. A device for processing signals, the device comprising:
a plurality of nodes, each node having an address that is unique; a plurality of processors, each processor uniquely assigned to a respective node of the plurality of nodes; and an interconnect bus having at least a first ring bus and a second ring bus, the interconnect bus configured to:
connect the plurality of nodes in a ring; androute data on at least one of the first ring bus or the second ring bus determined from a data type of the data to a node of the plurality of nodes according to the address assigned to the node, the data processed by the processor of the plurality of processors that is uniquely assigned to the node.