发明名称 |
General input/output architecture, protocol and related methods to implement flow control |
摘要 |
An enhanced general input/output communication architecture, protocol and related methods are presented. |
申请公布号 |
US9602408(B2) |
申请公布日期 |
2017.03.21 |
申请号 |
US201314144320 |
申请日期 |
2013.12.30 |
申请人 |
Intel Corporation |
发明人 |
Ajanovic Jasmin;Harriman David;Fanning Blaise;Lee David |
分类号 |
G06F15/16;H04L12/801;G06F13/12;G06F13/38;G06F13/42;G06F13/40;G06F5/06 |
主分类号 |
G06F15/16 |
代理机构 |
Patent Capital Group |
代理人 |
Patent Capital Group |
主权项 |
1. An apparatus, comprising:
a protocol stack including layers to communicate data over an interconnect, wherein the protocol stack is implemented at least in part in hardware circuitry and the layers comprise a physical layer, a data link layer, and a transaction layer; a transmitter to transmit data on a point to point interconnect; and wherein the protocol stack is to assemble a plurality of messages, and at least one of the messages comprises a data link layer message to include a plurality of credits fields, each of the plurality of credits fields corresponds to a respective one of a plurality of credit counters and is to indicate a respective number of credits to be returned for the corresponding credit counter, and the data link layer message does not encapsulate a transaction layer packet. |
地址 |
Santa Clara CA US |