发明名称 Sub-nanosecond distributed clock synchronization using alignment marker in ethernet IEEE 1588 protocol
摘要 A method for determining a slave clock to master clock time difference with an alignment marker. The method selects and transmits a first alignment marker at a first time by a transmitter that has a master clock in a first message to a receiver that has a slave clock. Subsequent to transmitting the first message, the method further transmits a second message that contains the first time and an identity of the first alignment marker. The method further receives the first message and records a second time that the first message is received. The method further receives the second message and the first time and the identity of the first alignment marker. The method further determines a transmission delay and generates a time difference from the slave clock to the master clock.
申请公布号 US9602271(B2) 申请公布日期 2017.03.21
申请号 US201514726945 申请日期 2015.06.01
申请人 GLOBALFOUNDRIES INC. 发明人 Benjamini Yiftach;Liu Yang;Song Cheng Wei;Yang Kai
分类号 H04L7/00 主分类号 H04L7/00
代理机构 代理人 Cai, Esq. Yuanmin
主权项 1. A method for determining a slave clock to master clock time difference with an alignment marker, the method comprising: receiving, by a processor, a first message that was sent at a first time and that includes a first alignment marker, wherein the processor has a slave clock, wherein the first alignment marker was selected by a computing device that has a master clock; recording, by the processor, a second time that the first message was received; receiving, by the processor, a second message that indicates the first time at which the first message was sent and an identity of the first alignment marker, wherein the second message was transmitted subsequent to the first message being transmitted; identifying, by the processor, the first alignment marker in a receiver based, at least in part, on the identity of the first alignment marker; determining, by the processor, a delay that is associated with data transmission between the receiver and a transmitter, the delay being determined based on information acquired during transmission of messages between the processor and the computing device; and generating, by the processor, a time difference from the slave clock to the master clock based, at least in part, on the delay, the first time, and the second time.
地址 Grand Cayman KY
您可能感兴趣的专利